Renesas?的低抖動時鐘發生器均是基于 PLL 的產品,因此可在一個應用中生成一個或多個時鐘信號。 此類產品包含的低相位噪聲振蕩器適用于大多數串行數據應用。 這些低抖動時鐘具有各種單端或差分信號級,如 LVCMOS、LVPECL、LVDS、HCSL、SSTL、HSTL 等。

一旦選定時鐘發生器,便可使用低加性相位噪聲扇出緩沖器來提供額外的拷貝和輸出類型。 Renesas?擁有業內最廣泛的低抖動時鐘和低相位噪聲振蕩器產品系列,適用于各種高度優化的解決方案。 對于應用特定型低抖動時鐘(如 PCIe、RF 和網絡同步),請點擊此處。

(提示: 如果需要不止一個唯一的輸出頻率(如 100MHz 和 125MHz),可使用“輸出庫”參數選擇器。 每個庫與唯一的輸出頻率對應。 每個庫的輸出數量有很大差異,取決于器件。)

低抖動時鐘/低相位噪聲振蕩器的主要參數

選擇用于特定應用的低抖動時鐘時,有許多重要的因素需要考慮。 用戶可以下列參數作為起始點,來縮小潛在解決方案的范圍:

  • 相位抖動:指在理想周期計時信號中不希望出現的偏差。 Renesas'?提供的低抖動時鐘的 RMS 相位抖動通常低于 700fs,在某些高性能應用中甚至低于 300fs。
  • 輸出頻率范圍:輸出頻率的有效范圍。 Renesas?提供低相位噪聲振蕩器來滿足所有主流應用的頻率需求。
  • 輸出類型:指低抖動時鐘所需輸出的信號類型。 Renesas?提供 CML、HCSL、HSTL、LVCMOS、LVDS、LVHSTL、LVPECL 和 LVTTL 等產品。
  • 核心電壓:為低相位噪聲振蕩器供電的電源電壓。 它通常由系統中可用的電源軌決定,并往往會對輸出的電壓電平產生影響。 Renesas’ 的低相位噪聲時鐘有 2.5V 和 3.3V 兩個版本。

關于低抖動時鐘(低相位噪聲振蕩器)
低抖動時鐘是能夠產生同步系統’操作所用計時信號的復雜 IC。 最基本的低抖動時鐘由諧振電路和放大器組成。 所產生的計時信號涵蓋范圍從簡單的 50% 占空比方波到更復雜的布置。 在此情況下,諧振電路通常是石英壓電低相位噪聲振蕩器。 Renesas?提供多個系列的低抖動時鐘,這些時鐘具有不同級別的功率、性能和靈活性,幾乎能滿足需要低相位噪聲振蕩器的任何應用的需求。

視頻和培訓

IDT VersaClock 5 Low Jitter Lab Demonstration

Description:

Lab demonstration and clock jitter measurement showing VersaClock 5. The frequency analyzer showing phase jitter at approximately 575 picoseconds RMS. Presented by Baljit Chandhoke, product manager at IDT. For more information about VersaClock, visit www.idt.com/go/VersaClock5

Transcript:

Hello, my name is Baljit Chandhoke, and I'm the Product Line Manager of timing products at IDT. Today, I will be giving you a brief lab demonstration of our new product, "VersaClock 5".

VersaClock 5 is a low power clock generator, with best in class jitter performance of 0.7 psec. It has extremely low power with core current consumption of only 30 MA. It is extremely programmable, and you can get any frequency you want at the output, up to 350MHz.

Now I'm going to start the lab demonstration. I have with me, an evaluation board. The evaluation board is powered by the USB cable, and is also used to control the VersaClock 5.

This is the Timing Commander software, which controls the VersaClock 5 device. As you see, I have it configured for 125MHz, LVPECL output, on Output 1.

On Output 2, I have it configured at 125MHz, HCSL output. Output 3, I have it configured at 156.25MHz LVDS, and Output 4 has 312.5MHz. All the outputs are operational and have different output frequencies.

Now, let's take a look at the performance. With all these outputs operational, and on Output 1, which is operating at 125MHz, I see 575 fsec RMS phase jitter from 12K to 20MHz.

This is industry leading in the power consumption of 30MA core in the space.

Now let's change the frequency, and see what happens to the phase noise. I'm going to change the frequency on Output 1 to 100MHz.

As you see, the frequency changed to 100MHz as shown on the screen, and the phase noise is still 576 fsec, from 12K to 20MHz. The noise floor is close to 150dBc.

So this product maintains the great performance, across a wide range of frequencies, as well as across multiple output types, and with different frequencies of the output.

So it provides you, a complete system solution, meeting the requirements of all your clocking needs in your system.